1. Field of the Invention
The present invention relates generally to a pipeline arithmetic apparatus. More particularly, the invention concerns a pipeline arithmetic apparatus which is capable of processing plural types of arithmetic operations in overlap.
2. Description of the Prior Art
In a pipeline arithmetic apparatus, the arithmetic operation is divided into a plurality of stages to be processed in an overlapping manner. To this end, arithmetic circuits are provided in correspondence to the individual states, respectively, to perform arithmetic operations in accordance with respective instructions, wherein the output of a given stage is supplied to the arithmetic circuit belonging to the suceeding stage. Although the hitherto known pipeline arithmetic apparatus is capable of processing plural sets of input data in overlapping fashion in a continuous manner for a single type of arithmetic operation, it can not execute continuously different types of arithmetic operations. In other words, until the processing of an arithmetic operation of one given type has been completed, the succeeding arithmetic operation of another type can not be initiated in an overlapping manner with the said one type arithmetic operation. For example, the hitherto known pipeline arithmetic apparatus can certainly execute floating-point addition continuously in an overlapping manner for plural sets of input data. However, it can not execute continuously the different types of arithmetic operations such as floating-point addition and fixed-point addition or floating-point subtraction in an overlapping manner with each other.
FIG. 1 of the accompanying drawings shows in a block diagram a typical known pipeline arithmetic apparatus which consists of three stages and includes three arithmetic circuits 2, 3 and 4. The data processing chain or data system of this pipeline arithmetic apparatus comprises an operand input register 1, intermediate stage latches 5 and 6, a register 7 for storing the results of the arithmetic operation and the arithmetic circuits 2, 3 and 4. Operands sent out from a storage 8 are supplied to the data system mentioned above through a data input bus 9, while the results of the arithmetic operation are stored in the storage 8 through a write-in bus 10. A main storage of associated computer system may be used as the storage 8 or alternatively the latter may be constituted by a group of data registers.
On the other hand, an operation code which indicates the type or content of the arithmetic operation for alternatively information which corresponds to the operation code (this information is referred to as the control information) is supplied from an instruction read-out circuit 18 to an instruction register 20 through an instruction activating bus 19 to be set therein in response to a set signal 22. The control information placed in the instruction register 20 is decoded by a decoder 21 which in turn responds to the control information to produce control signals for the data system or data processing chain such as latch set signals 11, 12, 13 and 14 and arithmetic operation control signals 15, 16 and 17.
FIG. 2 of the accompanying drawings shows time charts for illustrating two types of vector operations A and B executed continuously in the pipeline arithmetic apparatus shown in FIG. 1. The vector operations A and B concern the arithmetic operations of different types or contents. It is assumed that the arithmetic operations A and B are both executed for three sets of input data. In FIG. 2, numerals in circle .circle. , .circle. and .circle. represent element numbers of the operand vectors, respectively. As will be seen from FIG. 2, the operation A is executed continuously for the elements .circle. , .circle. and .circle. in overlap with one another. However, the contents of the instruction register 20 can not be altered until the result of aritmetic operation for the last inputted element .circle. of the arithmetic operation A has been outputted, thus involving three useless cycles (pipeline pitches) before the first element of the succeeding arithmetic operation B is allowed to be inputted.